1. Field of the Invention
The present invention pertains generally to electrical computers and more particularly to program products and methods for extracting and graphically or textually representing electronic circuit components and connections.
2. Description of Related Art
Modern electronic chip designers commonly employ circuit design representations to design and simulate electronic circuits. A traditional method of generating such design representations required circuit designers to connect logic symbols representing logic cell instances to specify a circuit design. Typically, a designer selected and placed the logic cell instances in a virtual design representation on a computer screen. The designer could then indicate connections between various logic cells by "drawing" lines connecting such logic symbols on the computer screen. The graphical representation of the design is referred to as a "circuit schematic". Furthermore, a non-graphical design representation may be generated from the schematic, including textual netlists and binary design databases. A netlist is typically a list of electronic logic cells with a description of the interconnections between the inputs and the outputs of the various logic cells instances. A popular netlist format is Electronic Design Interchange Format (EDIF), described in "Designer's Guide to EDIF", E. Marx et al., EDN 1987, and specified in "EDIF Electronic Design Interchange Format Version 200", ANSI/EIA Standard 548, specifically incorporated herein by reference for all that they teach and disclose. Generally, EDIF is a standardized netlist format, which has a LISP-like syntax and is intended to simplify data transfer between CAD/CAE systems.
A microelectronic circuit designer typically combines logic cells from a logic cell library to achieve the desired functionality in a circuit. A logic "cell" in the logic cell library can be defined by an EDIF netlist containing a cell model that specifies structural, functional and timing information. The cell model is typically defined, at least in part, by one or more "primitives". A primitive is a standard logic model, defined by a simulator vendor, that describes a fundamental logic block understood by a simulator (e.g., NAN2, AND2, etc.). A cell model designer uses primitives to develop a set of standard library cells for use by circuit designers. For example, a cell model designer might define an AND4 (i.e., a four input AND gate) library cell to comprise three AND2 (i.e., a two input AND gate) primitives. When a circuit design containing the AND4 cell is instantiated in a design and simulated, the simulator understands the operation of the AND4 based on its three AND2 primitives.
When a library cell is included (or instantiated) in a design, a "cell instance" is created in the design, which may also be defined by an EDIF netlist. A "design" refers to the hierarchical levels in a circuit design and typically includes a combination of component "cell instances" and/or "primitive instances". Each component cell instance may also include a combination of other cell instances and primitive instances. A single cell may be instantiated in a design multiple times, and each cell instance is typically given a unique identifier. Because an EDIF netlist may be hierarchical (i.e., represent many layers of circuitry), the unique identifier for the cell instance often includes a path name for defining the cell instance within the design hierarchy.
The circuit design terms used above may be analogized to a computer directory structure. The root computer directory is analogous to the "top" level of a circuit design hierarchy. In addition, a computer directory structure can have multiple layers of sub-directories within sub-directories. Likewise, an EDIF netlist for a design can have cell instances within cell instances (i.e., the design hierarchy). An individual sub-directory is typically defined by a unique directory path name; an individual cell instance is defined by a unique instance path name. A sub-directory may possess both files that terminate the directory path or subdirectories; a cell instance may possess both primitives that terminate the design hierarchy path or other cell instances.
Generally, the hierarchical nature of the EDIF format, its LISP-like syntax, and the inherent complexity of many circuit designs combine to form an EDIF netlist that is very complicated and difficult for a human to read, unless the user is very familiar with the design or experienced with the EDIF format. Accordingly, a need exists to simplify or translate the EDIF design representation to allow an EDIF-novice or a designer who is unfamiliar with a particular design to quickly understand the design, without requiring a detailed analysis of the EDIF netlist itself.